Antifuses are often used in programmable logic chips and write-once memories. Antifuses are usually located between conductive interconnects in an integrated circuit. The structure of an antifuse is typically an insulating layer sandwiched between two conductive layers. When manufactured, an antifuse has a very high resistance and can often be treated as an open circuit. An antifuse can be transformed, however, from its manufactured state into an element having a low resistance. A transformed antifuse can often be treated as a short circuit.
An antifuse may be transformed from a high resistance state to a low resistance state by applying a programming voltage between the two conducive layers across the insulating layer. The voltage gradient across the insulator causes a reaction between the insulator and one or both of the conductors which breaks down the insulator.
A method of manufacturing a conventional semiconductor device including an antifuse is described by Dixit et al. in U.S. Pat. No. 5,322,812. The manufacture of a conventional semiconductor apparatus 40 including an antifuse 45 having metal-insulator-metal layers is described with reference to FIG. 1. A first insulating layer 51 is formed on a substrate 50. A polysilicon layer 60 and then a metal silicide layer 66 are formed upon the first insulating layer 51. A second insulating layer 61 is deposited over the substrate 50, over the first insulating layer 51, and over the metal silicide layer 66. Holes are formed in the second insulating layer 61 by masking and etching. The antifuse 45 is formed in one hole, and standard contacts 46, 47 are formed in two additional holes.
A contact reflow and oxidation step rounds the edges of the second insulating layer 61 and forms an oxide layer (not shown) on the substrate 50 and on the silicide 66 in the holes in the second insulating layer 61. A mask is then used in removing the oxide layer from the hole for the antifuse 45.
An amorphous silicon layer 67 is then deposited over the second insulating layer 61 and in the holes in the second insulating layer 61. A mask and etch are used to remove the amorphous silicon layer 67 from the holes for the standard contacts 46, 47. The oxide layer is then removed from the holes for the standard contacts 46, 47 by etching. A barrier metal layer 68 and aluminum alloy layer 69 are then formed. The metal layers 68, 69 are then etched to define metal conducting lines for the antifuse 45 and standard contacts 46, 47.
The conventional method of manufacturing a semiconductor apparatus 40 including an antifuse 45 as described above uses masking and etching to form holes in second insulating layer 61, to remove the oxide layer from the antifuse 45, to remove the amorphous silicon layer 67 from the holes for the standard contacts 46, 47, and to define the conducting lines in the metal layers 68, 69. Each mask and etch is performed using lithography which is a relatively expensive step in manufacturing a semiconductor apparatus.
Capacitors are often used in integrated circuits. In many applications, as in analog-to-digital converters for example, it is desirable for capacitance not to vary with changes in voltage. A capacitor formed of metal-insulator-metal layers can provide a capacitance that does not vary with voltage. A conventional method of manufacturing a metal-insulator-metal capacitor is described by Radosevich et al. in U.S. Pat. No. 5,576,240.
A conventional method of manufacturing a semiconductor apparatus 5 including a capacitor 10 that is formed of metal-insulator-metal layers is described with reference to FIG. 2. A field oxide layer 11 is formed on a substrate 18. A polysilicon layer 12 is formed upon the field oxide layer 11 and an interlevel dielectric 13 is formed upon the field oxide layer 11 and the polysilicon layer 12. Openings are formed in the interlevel dielectric 13 in which a capacitor 10 and a contact via 19 are formed.
The bottom plate 14 is formed by depositing a titanium layer 14a and a titanium nitride layer 14b in the openings in the interlevel dielectric layer 13. The capacitor dielectric 15 is then deposited in both openings. The capacitor dielectric 15 is removed from the contact via 19 by masking and etching. An aluminum layer 17 is deposited. The aluminum layer 17 is then patterned by masking and etching.
The method of manufacturing a conventional semiconductor apparatus 5 including a capacitor 10 as described above uses masking and etching to remove the capacitor dielectric 15 from the contact via 19. Each mask and etch is performed using lithography which is a relatively expensive step in manufacturing a semiconductor apparatus.
To overcome the shortcomings of manufacturing a conventional antifuse or capacitor, a new method of manufacturing a conductor-insulator-conductor structure is provided. An object of the present invention is to provide an improved method of manufacturing a conductor-insulator-conductor semiconductor apparatus. A related object is to reduce the number of mask steps in manufacturing a conductor-insulator-conductor semiconductor apparatus. A further object is to reduce the cost of manufacturing a conductor-insulator-conductor semiconductor apparatus. Another object is to reduce the lithography steps in manufacturing a conductor-insulator-conductor semiconductor apparatus.